SH7763 Datasheet, PDF (644/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
20
TS2
0
R/W DMA Transfer Size Specify
With TS1 and TS0, this bit specifies the DMA transfer
size. When the transfer source or transfer destination is
a register of an on-chip peripheral module with a
transfer size set, a proper transfer size for the register
should be set. For the transfer source or destination
address specified by SAR or DAR, an address
boundary should be set according to the transfer data
size.
TS[2:0]
000: Byte units transfer
001: Word (2-byte) units transfer
010: Longword (4-byte) units transfer
011: 16-byte units transfer
100: 32-byte units transfer
Other than above: Setting prohibited
Rev. 1.00 Oct. 01, 2007 Page 578 of 1956
REJ09B0256-0100