SH7763 Datasheet, PDF (1666/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
Bit
Bit Name Initial Value R/W Description
31 to 28 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
27, 26 
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
25 to 4 SAU[25:4] All 0
R/W Start Address for Upper Display Data Fetch
The start address for data fetch of the display data
must be set within the synchronous DRAM area of
area 3.
3 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Notes: 1. The minimum alignment unit of LDSARU is 512 bytes when the hardware rotation
function is not used. Write 0 to the lower nine bits. When using the hardware rotation
function, set the LDSARU value so that the upper-left address of the image is aligned
with the 512-byte boundary.
2. When the hardware rotation function is used (ROT = 1), set the upper-left address of
the image which can be calculated from the display image size in this register. The
equation below shows how to calculate the LDSARU value when the image size is 240
× 340 and LDLAOR = 256. The LDSARU value is obtained not from the panel size but
from the memory size of the image to be displayed. Note that LDLAOR must be a
binary exponential at least as large as the horizontal width of the image. Calculate
backwards using the LDSARU value (LDSARU − 256 (LDLAOR value) × (320 − 1)) to
ensure that the upper-left address of the image is aligned with the 512-byte boundary.
LDSARU = (upper-left address of image) + 256 (LDLAOR value) × 319 (line)
Rev. 1.00 Oct. 01, 2007 Page 1600 of 1956
REJ09B0256-0100