SH7763 Datasheet, PDF (912/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Bit
5 to 0
Initial
Bit Name Value R/W
BSYSL0[5:0] 111111 R/W
Description
These bits set the threshold of the port 0-to-1 relay
FIFO size in 256-byte units when the TSU alerts the E-
MAC-0 that writing in the relay FIFO will be disabled
during relay operations.
H'00: 0 byte
H'01: 256 bytes
H'02: 512 bytes
:
:
H'29: 12,032 bytes
H'30: 12,288 bytes
Settings are disabled for H'31 to H'3F. (Alert is not
always carried out.)
When the data volume written in the relay FIFO
exceeds the threshold set in these bits, the TSU alerts
the E-MAC-0 that writing in the relay FIFO will be
disabled. Thereafter, alerting will be stopped when the
data volume written in the relay FIFO becomes 16
bytes smaller than this threshold.
When H'00 is set, the TSU always alerts the E-MAC-0
that writing to the relay FIFO will be disabled. When the
value set is equal to or higher than the port 0-to-1 relay
FIFO size set by bits FCM[2:0] in TSU_FCM, the TSU
does not alert the E-MAC-0 that writing in the relay
FIFO will be disabled.
This register must not be written to once after relay
operations have been enabled (after the FWEN0 bit in
TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set
to 1).
When the enable bit of relay operations (FWEN0 bit in
TSU_FWEN0 or FWEN1 bit in TSU_FWEN1) is cleared
to 0, the TSU stops alerting the E-MAC-0 that writing in
the relay FIFO will be disabled.
Rev. 1.00 Oct. 01, 2007 Page 846 of 1956
REJ09B0256-0100