SH7763 Datasheet, PDF (496/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
12.5 Operation
12.5.1 DDR-SDRAM Access
The DDR-SDRAM is accessed with a burst length of 2. Read or write commands that hit the page
are issued continuously and read data continuously.
Write command
ACT
WR WR WR WR
Write data
DDDDDDDD
read command
ACT
RD RD RD RD
read data
DDDDDDDD
Figure 12.4 DDR-SDRAM Access
12.5.2 DDR-SDRAM Initialization Sequence
Since the internal state of the DDR-SDRAM is undefined immediately after a power-on, initialize
the SDRAM according to the following sequence. Otherwise the device may be damaged.
An example of the initialization sequence for the DDR-SDRAM is shown below. For details, see
each memory manufacturer's datasheet.
1. Turn on the four power supplies to the DDR-SDRAM in the following order: VDD, VDDQ,
VREF, and VTT.
2. After the power supply, reference voltage, and clock are stabilized, maintain the current state
for at least 200 µs.
3. Perform a dummy read to any DDR-SDRAM address.
4. Set MIM to enable the DDR-SDRAM controller, set the endian mode, and so on.
5. Set SDR and STR.
6. Use the SMS field in SCR to enable the CKE pin.
7. Use the SMS field in SCR to issue the all-bank precharge (PREALL) command.
8. Use SDMR to issue the EMRS command and enable the DLL.
Rev. 1.00 Oct. 01, 2007 Page 430 of 1956
REJ09B0256-0100