SH7763 Datasheet, PDF (1868/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 42 User Debugging Interface (H-UDI)
42.4 Register Descriptions
The H-UDI has the following registers.
Table 42.3 Register Configuration (1)
CPU Side
Register Name
Abbrev.
Area P4
R/W Address*¹
Initial
Area 7 Address*¹ Size Value*²
Instruction register
SDIR
R H'FC11 0000 H'1C11 0000 16 H'0EFF
Interrupt source register SDINT R/W H'FC11 0018 H'1C11 0018 16 H'0000
Boundary scan register SDBSR  


Bypass register
SDBPR  


Notes: 1. The area P4 address is an address when accessing through area P4 in a virtual
address space. The area 7 address is an address when accessing through area 7 in a
physical space using the TLB.
2. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller
initializes to these values.
Table 42.4 Register Configuration (2)
H-UDI Side
Register Name
Abbrev. R/W
Size
Initial Value*¹
Instruction register
SDIR
R/W
32
H'FFFF FFFD (fixed value*²)
Interrupt source register SDINT W*³
32
H'0000 0000
Boundary scan register SDBSR 


Bypass register
SDBPR R/W
1
Undefined
Note: 1. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller
initializes to these values.
2. When reading via the H-UDI, the value is always H'FFFF FFFD.
3. Only 1 can be written to the LSB by the H-UDI interrupt command.
Table 42.5 Register Status in Each Processing State
Register Name
Abbrev.
Instruction register
SDIR
Interrupt source register SDINT
Power-On Reset Manual Reset Sleep
H'0EFF
Retained Retained
H'0000
Retained Retained
Standby
Retained
Retained
Rev. 1.00 Oct. 01, 2007 Page 1802 of 1956
REJ09B0256-0100