SH7763 Datasheet, PDF (428/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS1WCR can be selected.
When the burst ROM interface is used, a burst pitch number in the range of 0 to 7 is selectable
with bits BW[2:0] in CS1BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS1 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS1WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more.
(3) Area 2
For area 2, external address bits A28 to A26 are 010.
The interfaces that can be set for this area are the SRAM, MPX, burst ROM and DDR-SDRAM
interfaces.
When the SRAM interface is used, a bus width of 8, 16, or 32 bits is selectable with bits SZ[1:0]
in CS2BCR. When the MPX interface is used, a bus width of 32 bits should be selected through
bits SZ[1:0] in CS2BCR.
When area 2 is accessed, the CS2 signal is asserted (except for DDR-SDRAM area). In the case
where the SRAM interface is set, the RD signal, which can be used as OE, and write control
signals WE0 to WE3 are asserted.
As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS2WCR can be selected.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS2 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS2WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more.
When the DDR-SDRAM is used, see section 12, DDR-SDRAM Interface (DDRIF).
(4) Area 3
For area 3, external address bits A28 to A26 are 011.
This area is used only for the DDR-SDRAM interface.
Rev. 1.00 Oct. 01, 2007 Page 362 of 1956
REJ09B0256-0100