SH7763 Datasheet, PDF (823/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 Compare Match Timer (CMT)
21.3.4 DMA Transfer Requests and Internal Interrupt Requests to CPU
The setting of bits CMR1 and CMR0 in CMCSR selects the sending of a request for a DMA
transfer or for an internal interrupt to the CPU at a compare match.
A DMA transfer request has different specifications according to the CMT channel as described
below.
1. For channels 0 and 1, a single DMA transfer request is output at a compare match.
2. For channels 2 to 4, a DMA transfer request continues until the amount of data transferred has
reached the value set in the DMAC, and the output of the request then automatically stops.
To clear the interrupt request, the CMF bit should be set to 0. Set the CMF bit to 0 in the handling
routine for the CMT interrupt.
21.3.5 Compare Match Flag Set Timing (All Channels)
The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and
CMCNT match. The compare match signal is generated upon the final state of the match (timing
at which the CMCNT value is updated to H'0000). Consequently, after CMCOR and CMCNT
match, a compare match signal will not be generated until a CMCNT counter clock is input.
Figure 21.4 shows the set timing of the CMF bit.
Peripheral operating
clock (Pck0)
Counter clock
N+1
clock
CMCNT
N
0
CMCOR
N
Compare match signal
and interrupt signal
Figure 21.4 CMF Set Timing
Rev. 1.00 Oct. 01, 2007 Page 757 of 1956
REJ09B0256-0100