SH7763 Datasheet, PDF (703/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 Clock Pulse Generator (CPG)
16.3 Clock Operating Mode
Table 16.2 shows the relationship between the mode control pin (MD0, MD1, and MD2)
combinations and the clock operating mode after a power-on reset.
Table 16.2 Clock Operating Modes
External pin
Clock
EXTAL
combination*¹
operating
PLL PLL PLL frequency
mode MD2 MD1 MD0 1 2 3 (MHz)
Clock generated by CPG
Initial value
Ick SHck Bck Pck0 Pck1 DDRck of FRQCR
0
0 0 0 ON ON OFF 25 to 33.1 Frequency 8 4
22
1
4
H'1013 0035
ratio*²
Max.
266 133 66.6 66.6 33.3 133
frequency
Notes: 1. Mode pin (MD0, MD1, and MD2) combinations other than above are prohibited.
2. The ratio of the frequency of each clock to that of the crystal oscillator or the clock input
from the EXTAL pin.
Rev. 1.00 Oct. 01, 2007 Page 637 of 1956
REJ09B0256-0100