SH7763 Datasheet, PDF (485/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
Initial
Bit
Bit Name Value
R/W
28 to 16 DRI
H'0C34 R/W
15 to 12 LOCK
Undefined R
11, 10 
All 0
R
9
DRE
0
R/W
Description
DRAM Refresh Interval
When refreshing is valid (the DRE bit in MIM is set to
1), these bits specify the maximum refresh interval
(auto refresh). One count is the same as the cycle of
the memory clock. At 133-MHz operation, one count
corresponds to 7.5 ns. The minimum settable value is
H'020. When a value less than H'020 is set, H'020 is
added to the count value.
The DDRIF has a 13-bit internal counter. When the
DCE or DRE bit is cleared to 0, or the RMODE bit is
set to 1, this counter is cleared to 0. Otherwise, this
counter will increment by the external memory clock.
This counter is compared with the DRI bit. If a match
occurs, an auto-refresh request is generated in the
controller and auto-refreshing is performed. Note that
the counter is cleared to 0 at the match and then
begins incrementing again. The single auto-refresh
request that has been generated is recorded (max.).
When the DCE and DRE bits are set to 1 and the
RMODE bit is cleared to 0, an auto-refresh request is
not cleared until auto refreshing is performed. To set
this bit, the DRE bit should be cleared to 0 and should
be written to, and then 1 should be written to the DRE
bit. In this case, the previous written value should be
set to the DRI bits.
DLL Lock Status
These bits indicate the lock status of the DLL for
generating the read timing for the DDR-SDRAM. When
these bits are all set to 1, access to memory is
possible.
Reserved
These bits are always read as 0. The write value
should always be 0.
DRAM Refresh Enable
Sets whether the refresh mode is valid or invalid.
1: Valid
0: Invalid
Rev. 1.00 Oct. 01, 2007 Page 419 of 1956
REJ09B0256-0100