SH7763 Datasheet, PDF (856/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3 Register Descriptions
Table 23.2 shows the configuration of registers of the GETHER. Table 23.3 shows the state of
registers in each processing mode. The last number of the abbreviation of a register, except for
registers related to the CAM entry tables, corresponds to the number of the two Ethernet interface
ports (port 0 or port 1). Some numbers have been omitted in the text.
Table 23.2 Register Configuration
Name
Abbreviation R/W
Software reset register
ARSTR
R/W
E-MAC mode register
ECMR0
R/W
E-MAC status register
ECSR0
R/W
E-MAC interrupt permission register ECSIPR0 R/W
PHY interface register
PIR0
R/W
MAC address high register
MAHR0
R/W
MAC address low register
MALR0
R/W
Receive frame length register RFLR0
R/W
PHY status register
PSR0
R
PHY_INT polarity register
PIPR0
R/W
Transmit retry over counter register TROCR0
R/W
Delayed collision detect counter CDCR0
R/W
register
Lost carrier counter register
LCCR0
R/W
CRC error frame receive counter CEFCR0 R/W
register
Frame receive error counter register FRECR0
R/W
Too-short frame receive counter TSFRCR0 R/W
register
Too-long frame receive counter TLFRCR0 R/W
register
Residual-bit frame receive counter RFCR0
R/W
register
Carrier extension loss counter register CERCR0 R/W
P4 Area
Address
H'FEE0 1800
H'FEE0 0500
H'FEE0 0510
H'FEE0 0518
H'FEE0 0520
H'FEE0 05C0
H'FEE0 05C8
H'FEE0 0508
H'FEE0 0528
H'FEE0 052C
H'FEE0 0700
H'FEE0 0708
H'FEE0 0710
H'FEE0 0740
H'FEE0 0748
H'FEE0 0750
H'FEE0 0758
H'FEE0 0760
H'FEE0 0768
Area 7
Address
H'1EE0 1800
H'1EE0 0500
H'1EE0 0510
H'1EE0 0518
H'1EE0 0520
H'1EE0 05C0
H'1EE0 05C8
H'1EE0 0508
H'1EE0 0528
H'1EE0 052C
H'1EE0 0700
H'1EE0 0708
H'1EE0 0710
H'1EE0 0740
H'1EE0 0748
H'1EE0 0750
H'1EE0 0758
H'1EE0 0760
H'1EE0 0768
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Rev. 1.00 Oct. 01, 2007 Page 790 of 1956
REJ09B0256-0100