SH7763 Datasheet, PDF (1074/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
Initial
Bit
Bit Name Value
R/W Description
11, 10 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
LONG 0
R/W* Long Packet Reception Interrupt
0: Packet exceeding 188 or 192 bytes has not been
received
1: Packet exceeding 188 or 192 bytes has been received
When a packet exceeding 188 or 192 bytes is received,
the long packet counter and packet counter are both
incremented by one.
Data of 188 or 192 bytes is transferred to memory and
the excess data is discarded.
8
SHORT 0
R/W* Short Packet Reception Interrupt
0: Packet less than 188 or 192 bytes has not been not
received
1: Packet less than 188 or 192 bytes has been received
When a packet less than 188 or 192 bytes is received,
the short packet counter is incremented by one and the
packet is discarded.
7 to 5 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
ROVF 0
R/W* Receive FIFO Overflow Interrupt
0: Receive FIFO has not overflowed
1: Receive FIFO has overflowed
The packets already received are retained, but the
packet that caused overflow is discarded.
3 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
TSTO 0
R/W* Time Stamp Counter Overflow Interrupt
0: Time stamp counter has not cycled once after
receiving the last packet.
1: Time stamp counter has cycled once after receiving
the last packet.
Note: * Write 1 to clear the bit.
Rev. 1.00 Oct. 01, 2007 Page 1008 of 1956
REJ09B0256-0100