SH7763 Datasheet, PDF (136/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Table 3.6 Logic Operation Instructions
Instruction
Operation
AND Rm,Rn
Rn & Rm → Rn
AND #imm,R0
R0 & imm → R0
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm
→ (R0 + GBR)
NOT Rm,Rn
~Rm → Rn
OR Rm,Rn
Rn | Rm → Rn
OR #imm,R0
R0 | imm → R0
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm
→ (R0 + GBR)
TAS.B @Rn
When (Rn) = 0, 1 → T
Otherwise, 0 → T
In both cases,
1 → MSB of (Rn)
TST Rm,Rn
Rn & Rm;
when result = 0, 1 → T
Otherwise, 0 → T
TST #imm,R0
R0 & imm;
when result = 0, 1 → T
Otherwise, 0 → T
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;
when result = 0, 1 → T
Otherwise, 0 → T
XOR Rm,Rn
Rn ∧ Rm → Rn
XOR #imm,R0
R0 ∧ imm → R0
XOR.B #imm,@(R0,GBR) (R0 + GBR) ∧ imm
→ (R0 + GBR)
Instruction Code
Privileged T Bit
0010nnnnmmmm1001 —
—
11001001iiiiiiii —
—
11001101iiiiiiii —
—
New
—
—
—
0110nnnnmmmm0111 —
0010nnnnmmmm1011 —
11001011iiiiiiii —
11001111iiiiiiii —
—
—
—
—
—
—
—
—
0100nnnn00011011 —
Test —
result
0010nnnnmmmm1000 —
11001000iiiiiiii —
11001100iiiiiiii —
0010nnnnmmmm1010 —
11001010iiiiiiii —
11001110iiiiiiii —
Test —
result
Test —
result
Test —
result
—
—
—
—
—
—
Rev. 1.00 Oct. 01, 2007 Page 70 of 1956
REJ09B0256-0100