SH7763 Datasheet, PDF (26/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

28.3.3 Transmit Shift Register (SCTSR) ....................................................................... 1127
28.3.4 Transmit FIFO Data Register (SCFTDR)........................................................... 1127
28.3.5 Serial Mode Register (SCSMR).......................................................................... 1128
28.3.6 Serial Control Register (SCSCR)........................................................................ 1131
28.3.7 Serial Status Register (SCFSR) .......................................................................... 1135
28.3.8 Bit Rate Register (SCBRR) ................................................................................ 1141
28.3.9 FIFO Control Register (SCFCR) ........................................................................ 1142
28.3.10 FIFO Data Count Register (SCFDR).................................................................. 1144
28.3.11 Serial Port Register (SCSPTR) ........................................................................... 1145
28.3.12 Line Status Register (SCLSR) ............................................................................ 1147
28.3.13 BRG Frequency Division Register (BRGDL2) .................................................. 1148
28.3.14 BRG Clock Select Register (BRGCKS2) ........................................................... 1149
28.3.15 IrDA Serial Mode Register (SCSMRIR) ............................................................ 1150
28.4 Operation ......................................................................................................................... 1151
28.4.1 Overview ............................................................................................................ 1151
28.4.2 Operation in Asynchronous Mode ...................................................................... 1155
28.4.3 Operation in Clocked Synchronous Mode .......................................................... 1165
28.4.4 SCIF Interrupt Sources and the DMAC.............................................................. 1174
28.4.5 Usage Notes ........................................................................................................ 1176
28.5 Infrared Data Communication Interface .......................................................................... 1179
28.5.1 Infrared Data Communication Format................................................................ 1179
28.5.2 Operation of Infrared Data Communication Interface ........................................ 1180
28.6 Baud Rate Generator for External Clock (BRG) ............................................................. 1181
28.6.1 BRG Block Diagram........................................................................................... 1181
28.6.2 Restrictions on the BRG ..................................................................................... 1182
Section 29 Serial I/O with FIFO (SIOF) ......................................................... 1185
29.1 Features............................................................................................................................ 1185
29.2 Input/Output Pins............................................................................................................. 1187
29.3 Register Descriptions....................................................................................................... 1188
29.3.1 Mode Register (SIMDR) .................................................................................... 1192
29.3.2 Clock Select Register (SISCR) ........................................................................... 1194
29.3.3 Control Register (SICTR)................................................................................... 1196
29.3.4 Transmit Data Register (SITDR) ........................................................................ 1199
29.3.5 Receive Data Register (SIRDR) ......................................................................... 1200
29.3.6 Transmit Control Data Register (SITCR) ........................................................... 1201
29.3.7 Receive Control Data Register (SIRCR) ............................................................ 1202
29.3.8 Status Register (SISTR)...................................................................................... 1203
29.3.9 Interrupt Enable Register (SIIER) ...................................................................... 1209
29.3.10 FIFO Control Register (SIFCTR) ....................................................................... 1211
Rev. 1.00 Oct. 01, 2007 Page xxvi of lxvi