SH7763 Datasheet, PDF (58/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Caches
Table 7.1 Cache Features...................................................................................................... 187
Table 7.2 Store Queue Features ............................................................................................ 187
Table 7.3 Register Configuration.......................................................................................... 190
Table 7.4 Register States in Each Processing State .............................................................. 190
Section 8 L Memory
Table 8.1 L Memory Addresses............................................................................................ 217
Table 8.2 Register Configuration.......................................................................................... 218
Table 8.3 Register Status in Each Processing State .............................................................. 219
Table 8.4 Protective Function Exceptions to Access L Memory.......................................... 231
Section 9 Interrupt Controller (INTC)
Table 9.1 Interrupt Types........................................................................................................ 82
Table 9.2 INTC Pin Configuration ......................................................................................... 86
Table 9.3 INTC Register Configuration ................................................................................. 87
Table 9.4 Register States in Each Operating Mode ................................................................ 90
Table 9.5 Interrupt Request Sources and INT2PRI0 to INT2PRI13..................................... 113
Table 9.6 RL[3:0], IRL[7:4] Pins and Interrupt Levels ........................................................ 140
Table 9.7 Interrupt Exception Handling and Priority............................................................ 143
Table 9.8 Interrupt Response Time....................................................................................... 154
Table 9.9 Switching Sequence of IRQ7/IRL7 to IRQ0/IRL0 Pin Function ......................... 156
Section 10 SuperHyway Bus Bridge (SBR)
Table 10.1 Register Configuration.......................................................................................... 316
Table 10.2 Register State in Each Operating Mode................................................................ 316
Section 11 Local Bus State Controller (LBSC)
Table 11.1 Pin Configuration.................................................................................................. 324
Table 11.2 LBSC External Memory Space Map .................................................................... 327
Table 11.3 Setting of bus width for area 0.............................................................................. 330
Table 11.4 Correspondence between External Pin (MD5) and Endian .................................. 331
Table 11.5 PCMCIA Interface Features ................................................................................. 331
Table 11.6 PCMCIA Support Interface .................................................................................. 332
Table 11.7 Register Configuration.......................................................................................... 335
Table 11.8 Register State in Each Operating Made. ............................................................... 335
Table 11.9 32-Bit External Device/Big-Endian Access and Data Alignment......................... 359
Table 11.10 16-Bit External Device/Big-Endian Access and Data Alignment..................... 359
Table 11.11 8-Bit External Device/Big-Endian Access and Data Alignment ...................... 360
Table 11.12 32-Bit External Device/Little-Endian Access and Data Alignment.................. 361
Table 11.13 16-Bit External Device/Little-Endian Access and Data Alignment.................. 361
Table 11.14 8-Bit External Device/Little-Endian Access and Data Alignment.................... 362
Rev. 1.00 Oct. 01, 2007 Page lviii of lxvi