SH7763 Datasheet, PDF (614/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
After device 1 has claimed and granted the bus, and transferred data, the priority is as follows:
PCIC > device 0 > device 2 > device 3 > device 1
Then, after the PCIC has claimed and granted the bus, and transferred data, the priority is changed
to:
Device 0 > device 2 > device 3 > device 1 > PCIC
After device 3 has claimed and granted the bus, and transferred data, the priority is changed to:
Device 0 > device 2 > device 1 > PCIC > device 3
In host bus bridge mode, bus parking is always controlled by the PCIC.
(5) Interrupts
• 10 interrupts are available (these signals are connected to the INTC of this LSI)
• Interrupts are enabled/disabled and their priority levels are specified by the INTC of this LSI
• When the PCIC operates normal mode, INTA output is available to the host device on the PCI
bus. The INTA pin is specified assert or negate by the IOCS bit in the PCICR.
Table 13.6 Interrupt Priority
Signal
PCISERR
PCIINTA
PCIINTB
PCIINTC
PCIINTD
PCIEER
PCIPWD3
PCIPWD2
PCIPWD1
PCIPWD0
Interrupt Source
Priority
SERR assertion detected in host bus bridge mode
PCI interrupt A (INTA) detected in host bus bridge mode
PCI interrupt B (INTB) detected in host bus bridge mode
PCI interrupt C (INTC) detected in host bus bridge mode
PCI interrupt D (INTD) detected in host bus bridge mode
High
Error on PCI bus occurs and reflected in PCIIR and PCIAINT. The
interrupt can be masked.
Power state transition to D3 caused by PCIPINT. The interrupt can
be masked.
Power state transition to D2 caused by PCIPINT. The interrupt can
be masked.
Power state transition to D1 caused by PCIPINT. The interrupt can
be masked.
Power state transition to D0 caused by PCIPINT. The interrupt can
be masked.
Low
Rev. 1.00 Oct. 01, 2007 Page 548 of 1956
REJ09B0256-0100