SH7763 Datasheet, PDF (480/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
12.3.2 Data Alignment in Peripheral Modules
The endian mode in the DDRIF matches that in the CPU, and both big endian and little endian are
available.
Bit 31
Bit 0
DDR-SDRAM
32-bit
(Address A + 0)
(Address A + 4)
(Address A + 8)
(Address A + 12)
Example of memory address A[3:0] = (0000)
Other than the above, the DDRC wraps around the data
on command boundaries.
Time
Write
read
Little Wndian
64-bit width
63
32 31
0
(Address A + 4) (Address A + 0)
(Address A + 12) (Address A + 8)
Time
big endian
63
32 31
0
(Address A + 0) (Address A + 4)
Time
(Address A + 8) (Address A + 12)
Figure 12.2 Data Alignment in DDR-SDRAM and DDRIF
Rev. 1.00 Oct. 01, 2007 Page 414 of 1956
REJ09B0256-0100