SH7763 Datasheet, PDF (224/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
• C: Cacheability bit
Indicates whether a page is cacheable.
0: Not cacheable
1: Cacheable
When the control register area is mapped, this bit must be cleared to 0.
• D: Dirty bit
Indicates whether a write has been performed to a page.
0: Write has not been performed
1: Write has been performed
• WT: Write-through bit
Specifies the cache write mode.
0: Copy-back mode
1: Write-through mode
• 1-Kbyte page
Virtual address
31
10 9
0
VPN
Offset
• 4-Kbyte page
Virtual address
31
12 11
0
VPN
Offset
• 64-Kbyte page
Virtual address
31
16 15
0
VPN
Offset
• 1-Mbyte page
Virtual address
31
20 19
0
VPN
Offset
Physical address
28
10 9
0
PPN
Offset
Physical address
28
12 11
0
PPN
Offset
Physical address
28
16 15
0
PPN
Offset
Physical address
28
20 19
0
PPN
Offset
Figure 6.7 Relationship between Page Size and Address Format
Rev. 1.00 Oct. 01, 2007 Page 158 of 1956
REJ09B0256-0100