SH7763 Datasheet, PDF (691/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 External CPU Interface (EXCPU)
15.3.2 External CPU Memory Space Select Register (EXCMSETR)
EXCMSETR sets the base address used when the internal memory space of this LSI is accessed
by the external CPU.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−−−−−−−−−−− −−−−−
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− −−−−−− −−−−−
EXCMSET[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Bit
Bit Name
31 to 4 
Initial
Value
All 0
3 to 0 EXCMSET 0000
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Internal Memory Space Base Address
These bits set the base address of the memory space
used for access to the internal memory by the external
CPU.
The address of the memory space to be accessed is
comprised as follows:
31st and 30th bits: Fixed at B'01
29 to 26th bits: EXCMSET[3:0]
25 to 0th bits: Access address from the external CPU
The address range of the memory space accessible to
the external CPU is from H'4000 0000 to H'7FFF FFFF.
Rev. 1.00 Oct. 01, 2007 Page 625 of 1956
REJ09B0256-0100