SH7763 Datasheet, PDF (1800/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 40 General Purpose I/O (GPIO)
40.2.29 Port N Data Register (PNDR)
PNDR is an 8-bit readable/writable register that stores port N data.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
— PN5DT PN4DT PN3DT PN2DT PN1DT PN0DT
0
0 Pin state Pin state Pin state Pin state Pin state
R R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7

All0
R
Reserved
6
These bits are always read as 0, and the write value
should always be 0.
5
PN5DT
0
R/W Each of these bits stores output data for the
4
PN4DT
Pin state R/W
corresponding pin that is used as a general output port.
If the port is read, the value of the corresponding bit in
3
PN3DT
Pin state R/W this register will be read for a pin configured as a
2
PN2DT
Pin state R/W ^{general output port, while the state of the}
corresponding pin will be read for a pin configured as a
1
PN1DT
Pin state R/W _{general input port.}
0
PN0DT
Pin state R/W
Rev. 1.00 Oct. 01, 2007 Page 1734 of 1956
REJ09B0256-0100