SH7763 Datasheet, PDF (1083/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
(2) Clock Valid Reception (Input Data Rate: Max. 30 Mbps)
(a) Clock Valid Reception Interface
• Timing chart
Figure 25.3 shows the timing of the clock valid reception interface.
ST_CLK (input/output)
ST_START (input)
ST_VALID (input)
ST_REQ (input)
ST_D7 to ST_D0
(input/output)
Up to 8 bytes be received
Figure 25.3 Clock Valid Reception Timing
• I/O selection for ST_CLK pin
For the ST_CLK pin, input of an external clock or output of an internally generated clock can
be selected by the CKSL bit in STIMDR (maximum frequency is 33 MHz).
• Active level setting for ST_START, ST_VALID, and ST_REQ pins
The active levels of the ST_START, ST_VALID, and ST_REQ pins can be set by the STAT,
VLD, and REQ bits in STIMDR, respectively.
• Selection of ST_REQ pin usage
Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR.
When usage of the ST_REQ pin is enabled, the ST_REQ pin is asserted when the free space in
the transmit/receive FIFO for stream data becomes eight bytes or less. After assertion, up to
eight bytes of data can be received. The ST_REQ pin is negated when the free space in the
FIFO has become 192 bytes or more.
When usage of the ST_REQ pin is disabled, the ST_REQ pin output is fixed at low or high
depending on the REQ bit value.
Rev. 1.00 Oct. 01, 2007 Page 1017 of 1956
REJ09B0256-0100