SH7763 Datasheet, PDF (1534/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
35.3.5 HcInterruptEnable Register (USBHIE)
Writing 1 to a bit in this register sets the corresponding bit, while writing a 0 to a bit leaves the bit
unchanged.
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIE OC — — — — — — — — — — — — — —
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R/W R/W R R R R R R R R R R R R R R
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — RHSC FNO UE RD SF WDH SO
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
31
MIE
0
30
OC
0
29 to 7 
All 0
6
RHCS
0
5
FNO
0
4
UE
0
3
RD
0
R/W Description
R/W MasterInterruptEnable
This bit is a global interrupt enable. Writing 1 allows
interrupts to be enabled via the specific enable bits
listed below.
R/W OwnershipChangeEnable
0: Ignored
1: Interrupt due to Ownership Change is enabled.
R
Reserved
These bits are always read as 0. The write value should
always be 0
R/W RootHubStatusChangeEnable
0: Ignored
1: Interrupt due to Root Hub Status Change is enabled.
R/W FrameNumberOverflowEnable
0: Ignored
1: Interrupt due to Frame Number Overflow is enabled.
R/W UnrecoverableErrorEnable
This function is not supported. Writing is ignored.
R/W ResumeDetectedEnable
0: Ignored
1: Interrupt due to Resume Detected is enabled.
Rev. 1.00 Oct. 01, 2007 Page 1468 of 1956
REJ09B0256-0100