SH7763 Datasheet, PDF (1593/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.18 EP0s Data Register (EPDR0s)
EPDR0s is a data register specifically for endpoint 0 setup command. EPDR0s holds 8-byte
command data sent in the setup stage. However, only the command to be processed by a
microprocessor (firmware) is received. The command data to be processed automatically by this
module is not stored.
Since the setup command mast be received, previous data in the buffer is over written with new
data. In other words, when the reception of data in the setup stage starts during read, reception has
priority and read data is invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————
D[7:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
Initial Value R/W Description
31 to 8 
Undefined R Reserved
These bits are always read as undefined value.
7 to 0 D[7:0]
Undefined R
Data register for storing the setup command at the
control-out transfer
Note: The EPDR0s register should be read in longword units or eight consecutive times in byte
units. If reading is stopped before it completes, data received in the subsequent setup stage
is not read successfully.
Rev. 1.00 Oct. 01, 2007 Page 1527 of 1956
REJ09B0256-0100