SH7763 Datasheet, PDF (1110/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
26.4 Operations
26.4.1 Data and Clock Filters
These blocks filter out glitches on signals coming from the I²C bus. Glitches up to one internal
clock period in width are rejected (For details on the internal clock frequency see section 26.3.9,
Clock Control Register (ICCCR)). This is for the faster I²C bit rate (400 KHz) but does not violate
the slower I²C bus rate specification.
These blocks also resynchronizes bus signals with the internal clock.
26.4.2 Clock Generator
The clock generator has two functions. Firstly, it generates the SCL I²C bus clock according to
commands from of the master or slave interface. Secondly, it controls the internal clock rate, used
by filtering blocks and the master and slave interfaces. This clock functions as a clock enable
signal of the registers in these blocks.
26.4.3 Master/Slave Interfaces
These two interfaces run independently and in parallel. The master interface controls the
transmission of address and data on the I²C bus. The slave interface monitors the I²C bus and takes
part in transmissions if its programmed address is seen on the bus. The interfaces communicate
with the control/status registers independently. There is only one interrupt line output from the I²C
module. The interrupt source is either the master or the slave.
26.4.4 Software Status Interlocking
In order that the software interface to the I²C module be as robust as possible, various status
interlocks are built into the operation of the master and slave interfaces. The status bits involved
are:
(1) MDR and SDR
MDR and SDR are set to 1 when data is received. Clear the status after reading the receive data
register. If data is received while MDR and SDR are set, hardware recognizes that unread data
remains in the receive data register and automatically holds SCL at low level and suspends data
transmission. In this case, transmission can be resumed by clearing the status after reading the
receive data.
Rev. 1.00 Oct. 01, 2007 Page 1044 of 1956
REJ09B0256-0100