SH7763 Datasheet, PDF (1214/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.13 BRG Frequency Division Register (BRGDL2)
BRGDR2 specifies the division ratio of the division clocks generated by the BRG. The clock
division ratio set in this register can be determined with the following equation.
Clock division ratio = clock input frequency/(required baud rate × 16)
Table 28.5 shows the clock division ratios when a 3.686 MHz crystal resonator is used.
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BRGDL[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0
Bit Name
BRGDL
[15:0]
Initial
Value
All 0
R/W Description
R/W Division Ratio of BRG Generated Clock
These bits specify the division ratio of the division
clocks generated by the BRG.
A division ratio from 1 to 65535 can be specified.
Table 28.5 Baud Rate (3.6864 MHz Clock)
Baud Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
Division Ratio
4608
3072
2095
1713
1536
768
384
192
128
115
96
64
Error Rate*


−0.022
0.001





0.174


Rev. 1.00 Oct. 01, 2007 Page 1148 of 1956
REJ09B0256-0100