SH7763 Datasheet, PDF (721/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
(2) Manual reset
1. Reset sources
• Input low level via MRESET pin.
• When a general exception other than a user break occurs while the BL bit is set to 1 in SR
• When the WDTCNT overflows while the WT/IT bit and the RSTS bit are set to 1 in WTCSR.
2. Branch destination address: H’A000 0000
3. Operation in branch
Exception code H’020 is set in the EXPEVT register. The VBR and SR registers are initialized,
and the program branches to PC =H’A000 0000. By initialization, the VBR register is set to
H’0000 0000. In the SR register, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0,
and the IMASK3 to IMASK0 bits (interrupt mask level) are set to B’1111.
The CPU and the peripheral modules are also initialized. For details, see the register descriptions
in each section.
Manual_reset()
{
EXPEVT = H'0000 0020;
VBR = H'0000 0000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A000 0000;
}
17.4.2 Using watchdog timer mode
1. Set the WDTCNT overflow interval value in WDTST.
2. Set the WT/IT bit in WDTCSR to 1, select the type of reset with the RSTS bit.
3. When the TME bit in WDTCSR is set to 1, the WDT count starts.
Rev. 1.00 Oct. 01, 2007 Page 655 of 1956
REJ09B0256-0100