SH7763 Datasheet, PDF (678/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
Figure 14.17 shows the timing of the TEND output.
CLKOUT
Bus cycle
DMAC
Last DMA transfer
CPU
DMAC
CPU
CPU
DREQ
DACK
(Active-high)
TEND
(Active-high)
Figure 14.17 DMA Transfer End Signal (Cycle Steal Mode Level Detection)
Note that the DACK output and TEND output are divided to align the data when an 8-bit or 16-bit
external device is accessed in longword units, or when an 8-bit external device is accessed in word
units. This example is shown in figure 14.18.
Rev. 1.00 Oct. 01, 2007 Page 612 of 1956
REJ09B0256-0100