SH7763 Datasheet, PDF (1389/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.22 Switch Status Register (SWSR)
SWSR controls the peripheral clock 1 and the internally divided clock when the card is identified.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
GATE_
CDB
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R
R
Bit
7 to 3
2
1, 0
Initial
Bit Name Value R/W

All 0 R
GATE_CDB 0
R/W

All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Clock Control at Card Identification
Stops the clock supply to FF that is not required at card
identification
0: Peripheral clock 1 and internal divided clock
operating
1: Peripheral clock 1 and internal divided clock halted
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1323 of 1956
REJ09B0256-0100