SH7763 Datasheet, PDF (1019/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
a different receive buffer specified by a different receive descriptor. Thus, one receive frame can
be stored in multiple receive buffers.
Figure 23.6 shows the relationship between the receive descriptors and receive buffers.
Receive descriptor ring
(in memory)
Receive buffer
(in memory)
RACT
RDL
RFP[1:0]
00 1 1
Transmit descriptor 1
(Transmit frame A)
00 1 0
Transmit descriptor 2
(Transmit frame B)
00 0 1
Transmit descriptor 3
(Transmit frame B)
00 1 1
Transmit descriptor 4
(Transmit frame C)
00 1 1
Transmit descriptor 5
(Transmit frame D)
10 - -
Transmit descriptor 6
(Waiting for a receive frame)
10 - -
Transmit descriptor 7
(Waiting for a receive frame)
11 - -
Transmit descriptor 8
(Waiting for a receive frame)
4 bytes
32-bytes
boundary
32-bytes
boundary
32-bytes
boundary
Receive frame A
(29 bytes)
(Underfined value)
32 bytes of
unused area
32-bytes
boundary
32-bytes
boundary
Receive frame B
(Former 32 bytes)
32-bytes
boundary
32-bytes
boundary
Receive frame B
(Former 32 bytes)
32-bytes
boundary
Padding data
32-bytes
boundary
Receive frame C
(53 bytes)
32-bytes
boundary
32-bytes
boundary
32-bytes
boundary
Receive frame D
(Former 29 bytes)
32-bytes
boundary
32-bytes
boundary
Padding data
Receive frame D
(Latter 35 bytes)
32-bytes
boundary
Receive frame data
(A frame input from the GMII/MII/RMIi is
written to the receive FIFO. Then the frame
is transferred by DMA transfer from the
receive FIFO to the receive buffer in memory.)
Receive frame A
29 bytes
When the receive frame ;ength is not a multiple
of 32 bytes, an undefined value is written.
Receive frame B
63 bytes
This frame is divided into two descriptor and
stored
Receive frame C
53 bytes
When padding data is inserted at the top of
the receive frame. the receive frame can be
written to arbitrary byte boundary in memory.
Receive frame D
64 bytes
When padding data is inserted in the middle
of the receive frame, PRADIR should be set
so that the latter half of data is written from
to the 4-bytes boundary in the receive buffer.
Figure 23.6 Relationship between Receive Descriptor and Receive Buffer
Rev. 1.00 Oct. 01, 2007 Page 953 of 1956
REJ09B0256-0100