SH7763 Datasheet, PDF (134/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Table 3.5 Arithmetic Operation Instructions
Instruction
Operation
ADD
Rm,Rn Rn + Rm → Rn
ADD
#imm,Rn Rn + imm → Rn
ADDC
Rm,Rn Rn + Rm + T → Rn,
carry → T
ADDV
Rm,Rn Rn + Rm → Rn,
overflow → T
CMP/EQ #imm,R0 When R0 = imm, 1 → T
Otherwise, 0 → T
CMP/EQ Rm,Rn When Rn = Rm, 1 → T
Otherwise, 0 → T
CMP/HS Rm,Rn
When Rn ≥ Rm (unsigned),
1→T
Otherwise, 0 → T
CMP/GE Rm,Rn
When Rn ≥ Rm (signed),
1→T
Otherwise, 0 → T
CMP/HI
Rm,Rn
When Rn > Rm (unsigned),
1→T
Otherwise, 0 → T
CMP/GT Rm,Rn
When Rn > Rm (signed),
1→T
Otherwise, 0 → T
CMP/PZ Rn
When Rn ≥ 0, 1 → T
Otherwise, 0 → T
CMP/PL Rn
When Rn > 0, 1 → T
Otherwise, 0 → T
CMP/STR Rm,Rn
When any bytes are equal,
1→T
Otherwise, 0 → T
DIV1
Rm,Rn 1-step division (Rn ÷ Rm)
DIV0S Rm,Rn
DIV0U
DMULS.L Rm,Rn
MSB of Rn → Q,
MSB of Rm → M, M^Q → T
0 → M/Q/T
Signed,
Rn × Rm → MAC,
32 × 32 → 64 bits
Instruction Code
Privileged T Bit
0011nnnnmmmm1100 —
—
0111nnnniiiiiiii —
—
0011nnnnmmmm1110 —
Carry
New
—
—
—
0011nnnnmmmm1111 —
Overflow —
10001000iiiiiiii —
0011nnnnmmmm0000 —
0011nnnnmmmm0010 —
Comparison —
result
Comparison —
result
Comparison —
result
0011nnnnmmmm0011 —
Comparison —
result
0011nnnnmmmm0110 —
Comparison —
result
0011nnnnmmmm0111 —
Comparison —
result
0100nnnn00010001 —
0100nnnn00010101 —
0010nnnnmmmm1100 —
Comparison —
result
Comparison —
result
Comparison —
result
0011nnnnmmmm0100 —
0010nnnnmmmm0111 —
0000000000011001 —
0011nnnnmmmm1101 —
Calculation —
result
Calculation —
result
0
—
—
—
Rev. 1.00 Oct. 01, 2007 Page 68 of 1956
REJ09B0256-0100