SH7763 Datasheet, PDF (1264/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Bit
7 to 2
1
0
Initial
Bit Name Value R/W Description
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
TXRST 0
R/W Transmit Reset
0: Does not reset transmit operation
1: Resets transmit operation
• This bit setting becomes valid immediately. For
details of transmit reset, refer to table 29.13.
• SIOF automatically clears this bit upon the
completion of reset. Thus, this bit is always read as
0.
RXRST 0
R/W Receive Reset
0: Does not reset receive operation
1: Resets receive operation
• This bit setting becomes valid immediately. For
details of receive reset, refer to table 29.13.
• SIOF automatically clears this bit upon the
completion of reset. Thus, this bit is always read as
0.
Rev. 1.00 Oct. 01, 2007 Page 1198 of 1956
REJ09B0256-0100