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SH7763 Datasheet, PDF (98/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series
Section 1 Overview
Pin No. Pin Name
I/O
AB11 PTB2/AD11/PINT10/LCDM_D7 IO/IO/I/O
AB12
PTB6/CBE0/PINT14/
LCDM_D3
IO/IO/I/O
AB13 PTC1/AD4/LCDM_D1
IO/IO/O
AB14
AB15
AB16
AB17
VSSQ
VCCQ
MPMD
PTO6/IRQ0/IRL0/
DACK1M/MD5


I
IO/I/I/O/I
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AC1
PTO2/AUDATA1/
RMII0M1_MDC
VSSQ
TDO
VSSQ
VSSQ
VCCQ
AN3
AN2
PTH6/AD27/TPU_TO2/
ET1_CRS/RMII1M_TXD_EN
IO/O/O

O



I
I
IO/IO/O/I/O
AC2 PTH0/AD25/TPU_TI3A/
ET1_COL/RMII1M_RX_ER
IO/IO/I/I/I
AC3 VSSQ

AC4 VCCQ

AC5 PTH1/IDSEL/TPU_TI3B/
IO/I/I/I/I
ET1_RX-ER/RMII1M_CRS_DV
Function
Power
Supply
Port/PCI address-and-data bus/port VCCQ
interrupt input/LCD data (mirror pin)
Port/PCI command and byte
enable/port interrupt input/LCD data
(mirror pin)
VCCQ
Port/PCI address-and-data bus/LCD VCCQ
data (mirror pin)
I/O GND

I/O VCC

Chip mode specification
VCCQ
Port/external interrupt input/DMA
VCCQ
transfer request acknowledge (mirror
pin)/mode control (endian switching)
Port/AUD data/RMII management
data clock
VCCQ
I/O GND

H-UDI data output
VCCQ
I/O GND

I/O GND

I/O VCC

Analog input
AVcc
Analog input
AVcc
Port/PCI address-and-data bus/TPU
clock output/ETHER carrier
detection/RMII transmit enable
(mirror pin)
VCCQ
Port/PCI address-and-data bus/TPU
clock input/ETHER collision
detection/RMII receive error (mirror
pin)
VCCQ
I/O GND

I/O VCC

Port/PCI configuration device
select/TPU clock input/ETHER
receive error/RMII carrier detection
(mirror pin)
VCCQ
Rev. 1.00 Oct. 01, 2007 Page 32 of 1956
REJ09B0256-0100