SH7763 Datasheet, PDF (567/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(9) PCI Error Command Information Register (PCICIR)
This register records the PCI command information when an error is detected.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTEM —
—
—
—
RW
TET
—
—
—
—
—
—
—
—
—
—
Initial value: — 0
0
0
0—0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————
ECL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0 ————
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31
MTEM
30 to 27 
26
RWTET
25 to 4 
3 to 0 ECL
Initial
Value
Undefined
All 0
Undefined
All 0
Undefined
R/W Description
SH: R Master Error
PCI: R Indicates that an error has occurred during a master
access.
0: Master error does not occur
1: Master error occurs
SH: R Reserved
PCI: R These bits are always read as 0. The write value
should always be 0.
SH: R Target Error
PCI: R Indicates that an error has occurred during a target
read or a target write access.
0: Target error does not occur
1: Target error occurs
SH: R Reserved
PCI: R These bits are always read as 0. The write value
should always be 0.
SH: R Command Log
PCI: R Hold PCI command information (the state of the
CBE[3:0] signal) when an error occurs.
Rev. 1.00 Oct. 01, 2007 Page 501 of 1956
REJ09B0256-0100