SH7763 Datasheet, PDF (722/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
4. During operation in watchdog timer mode, clear to the WDTCNT or WDTBCNT periodically
so that WDTCNT does not overflow. See section 17.4.5, Clearing WDT Counter for WDT
counter clear method.
5. When the WDTCNT overflows, the WDT sets the WOVF flag in WDTCSR to 1, and
generates a reset of the type specified by the RSTS bit. After reset operation, the WDTCNT
and WDTBCNT continue counting again.
17.4.3 Using Interval timer mode
When the WDT is operating in interval timer mode, an interval timer interrupt is generated each
time the counter overflows. This enables interrupts to be generated at fixed intervals.
1. Set the WDTCNT overflow time in WDTST.
2. Clear the WT/IT bit in WDTCSR to 0.
3. When the TME bit in WDTCSR is set to 1, the WDT count starts.
4. When the WDTCNT overflows, the WDT sets the IOVF flag in WDTCSR to 1, and sends an
interval timer interrupt (ITI) request to INTC. The counter continues counting.
17.4.4 Time for WDT Overflow
Figure 17.2 shows a WDT counting up operation.
In interval timer mode, the WDT continues counting even after the WDTCNT overflow. In
watchdog timer mode, the WDT clears the WDTCNT and WDTBCNT and start counting again
after reset operation.
Rev. 1.00 Oct. 01, 2007 Page 656 of 1956
REJ09B0256-0100