SH7763 Datasheet, PDF (177/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
Exception Transition
Direction*³
Exception Execution
Category Mode
Exception
Priority Priority Vector
Level*² Order*² Address
Exception
Offset Code*⁴
General Completion Unconditional trap (TRAPA) 2
exception type
User break after instruction
2
execution*¹
4
(VBR)
H'100 H'160
10
(VBR/DBR) H'100/— H'1E0
Interrupt Completion Nonmaskable interrupt
3
—
(VBR)
H'600 H'1C0
type
General interrupt request
4
—
(VBR)
H'600 —
Notes: 1. When UBDE in CBCR = 1, PC = DBR. In other cases, PC = VBR + H'100.
2. Priority is first assigned by priority level, then by priority order within each level (the
lowest number represents the highest priority).
3. Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases.
4. Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
Rev. 1.00 Oct. 01, 2007 Page 111 of 1956
REJ09B0256-0100