SH7763 Datasheet, PDF (348/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W
31 to 26 —
All 0 R
25
24
23, 22
SCIF2
USBF
—
0
R/W
0
R/W
All 0 R
21
20
19, 18
STIF1
STIF0
—
0
R/W
0
R/W
All 0 R
17
USBH
0
R/W
16
GETHER 0
R/W
15
PCC
14, 13 —
0
R/W
All 0 R
12
ADC
0
R/W
11
TPU
0
R/W
10
SIM
0
R/W
9
SIOF2
0
R/W
8
SIOF1
0
R/W
7
LCDC
0
R/W
6
—
0
R
5
IIC1
0
R/W
4
IIC0
0
R/W
3
SSI3
0
R/W
2
SSI2
0
R/W
Function
Description
These bits are always read as Clears interrupt
0. The write value should
masking for each
always be 0
peripheral module.
Clears SCIF2 interrupt masking [When writing]
Clears USBF interrupt masking 0: Invalid
These bits are always read as
0. The write value should
always be 0
1: Interrupt mask is
cleared
[When reading]
Clears STIF1 interrupt masking _{Always 0}
Clears STIF0 interrupt masking
These bits are always read as
0. The write value should
always be 0
Clears USBH interrupt masking
Clears GETHER interrupt
masking
Clears PCC interrupt masking
These bits are always read as
0. The write value should
always be 0
Clears ADC interrupt masking
Clears TPU interrupt masking
Clears SIM interrupt masking
Clears SIOF2 interrupt masking
Clears SIOF1 interrupt masking
Clears LCDC interrupt masking
This bit is always read as 0.
The write value should always
be 0
Clears IIC1 interrupt masking
Clears IIC0 interrupt masking
Clears SSI3 interrupt masking
Clears SSI2 interrupt masking
Rev. 1.00 Oct. 01, 2007 Page 282 of 1956
REJ09B0256-0100