SH7763 Datasheet, PDF (572/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Bit
13
12
11
10 to 4
3
2
1
0
Bit Name
MBIM
TBTOIM
MBTOIM

TAIM
MAIM
RDPEIM
WDPEIM
Initial
Value
0
0
0
All 0
0
0
0
0
R/W
Description
SH: R/WC Master-Broken Interrupt Mask
PCI: R
0: PCIAINT.MBI disabled (masked)
1: PCIAINT.MBI enabled (not masked)
SH: R/WC Target Bus Time-Out Interrupt Mask
PCI: R
0: PCIAINT.TBTOI disabled (masked)
1: PCIAINT.TBTOI enabled (not masked)
SH: R/WC Master Bus Time-Out Interrupt Mask
PCI: R
0: PCIAINT.MBTOI disabled (masked)
1: PCIAINT.MBTOI enabled (not masked)
SH: R
Reserved
PCI: R
These bits are always read as 0. The write value
should always be 0.
SH: R/WC Target-Abort Interrupt Mask
PCI: R
0: PCIAINT.TAI disabled (masked)
1: PCIAINT.TAI enabled (not masked)
SH: R/WC Master-Abort Interrupt Mask
PCI: R
0: PCIAINT.MAI disabled (masked)
1: PCIAINT.MAI enabled (not masked)
SH: R/WC Read Data Parity Error Interrupt Mask
PCI: R
0: PCIAINT.RDPEI disabled (masked)
1: PCIAINT.RDPEI enabled (not masked)
SH: R/WC Write Data Parity Error Interrupt Mask
PCI: R
0: PCIAINT.WDPEI disabled (masked)
1: PCIAINT.WDPEI enabled (not masked)
Rev. 1.00 Oct. 01, 2007 Page 506 of 1956
REJ09B0256-0100