SH7763 Datasheet, PDF (594/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
13.4.2 PCIC Initialization
After a power-on reset, the PCIC enable bit (ENBL) of the PCIC enable control register (PCIECR)
and the internal register initialization bit (CFINIT) of the PCI control register (PCICR) is cleared.
At this point, if the PCIC is operating as the PCI bus host (host bus bridge mode), the bus
privileges are permanently granted to the PCIC, and no device arbitration is performed on the PCI
bus. When the PCIC is not operating as host (normal mode), retries are returned without accepting
access from PCI external devices connected to the PCI bus. In addition, all accesses to the PCIC
from the CPU are invalid except the access to the PCIECR if the PCIECR.ENBL is cleared to 0. A
write access is invalid and a read access will read 0, none of the registers can be modified, and any
access to the PCI bus will not be executed.
To initialize the PCIC, first setting the enable bit in the PCIECR to 1. The PCIC's internal
configuration registers and local registers must be initialized before setting the CFINIT bit in the
PCICR to 1 (while the CFINIT bit is cleared to 0). On completion of initialization, set the CFINIT
bit to 1. When operating as host, arbitration is enabled; when operating as non-host, the PCIC can
be accessed from the PCI bus.
Regardless of whether the PCIC is operating as the host or normal, external PCI devices cannot be
accessed from the PCIC while the CFINIT bit is being cleared. Set the CFINIT bit to 1 before
accessing an external PCIC device.
Be sure to initialize the following registers while the CFINIT bit is being cleared (before setting to
1): PCI command (PCICMD), PCI status (PCISTATUS), PCI sub system vender ID (PCISVID),
PCI subsystem ID (PCISID), PCI local space register 0/1 (PCILSR 0/1) and PCI local address
register 0/1.
Rev. 1.00 Oct. 01, 2007 Page 528 of 1956
REJ09B0256-0100