SH7763 Datasheet, PDF (481/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
12.4 Register Descriptions
Table 12.4 shows the DDRIF registers.
These registers should be set when access is not made to the DDR-SDRAM from peripheral
modules. When the access is not made and the DCE bit (DDR-SDRAM control enable) in the
memory interface mode register is cleared to 0 or the SELFS bit (self-refresh status) in that
register is set to 1, set other registers.
Although the bit width for registers is 64 bits, access the registers in longwords (32 bits). Writing
to this register is reflected in longwords. Reading this register returns a current longword value. In
big endian mode, when accessing bits 63 to 32, specify address 8n + 0. When accessing bits 31 to
0, specify address 8n + 4.
Table 12.4 Register Configuration
Register Name
Area P4
Abbreviation R/W Address*¹
Area 7
Address*¹
Access
Size
Memory interface mode register MIM
R/W H'FE80 0008 H'1E80 0008 32
DDR-SDRAM control register SCR
R/W H'FE80 0010 H'1E80 0010 32
DDR-SDRAM timing register STR
R/W H'FE80 0018 H'1E80 0018 32
DDR-SDRAM row attribute
register
SDR
R/W H'FE80 0030 H'1E80 0030 32
DDR-SDRAM mode register SDMR
(W) H'FE9x xxxx*² H'1E9x xxxx*² 32
DDR-SDRAM back-up register DBK
R
H'FE80 0400 H'1E80 0400 32
Notes: 1. P4 addresses are used when area P4 in the virtual address space is used, and area 7
addresses are used when accessing the register through area 7 in the physical address
space using the TLB.
2. For details, see section 12.4.5, DDR-SDRAM Mode Register (SDMR).
Rev. 1.00 Oct. 01, 2007 Page 415 of 1956
REJ09B0256-0100