SH7763 Datasheet, PDF (174/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
5.2.3 Interrupt Event Register (INTEVT)
The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is
set automatically by hardware when an exception occurs. INTEVT can also be modified by
software.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
R/W: R
Bit: 15
Initial value: 0
R/W: R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
INTCODE
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 14 
13 to 0 INTCODE
Initial
Value R/W
All 0
R
Undefined R/W
Description
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
Exception Code
The exception code for an interrupt is set. For details,
see table 5.3.
Rev. 1.00 Oct. 01, 2007 Page 108 of 1956
REJ09B0256-0100