SH7763 Datasheet, PDF (1464/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Audio Codec Interface (HAC)
33.3.3 Command/Status Data Register (HACCSDR)
HACCSDR is a 32-bit read/write data register used for accessing the codec register. Write the
command data to HACCSDR. The HAC then transmits the data to the codec via slot 2.
After the codec has responded to a read request (HACRSR.STDRY = 1), the status data received
via slot 2 can be read out from HACCSDR. In both read and write, HACCSAR stores the related
codec register address.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− − −− − − − −− −− −
CD/SD[15:12]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CD/SD[11:0]
− −− −
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Bit
Bit Name
31 to 20 
Initial
Value R/W
All 0 R
19 to 4 CD/SD[15:0] All 0 R/W
3 to 0 
All 0 R
Description
Reserved
Always 0 for read and write.
Command Data 15 to 0/Status Data 15 to 0
Write data to these bits and then write the codec
register address in HACCSAR. The HAC then transmits
the data to the codec.
Read these bits to get the contents of the codec
register indicated by HACCSAR.
Reserved
Always 0 for read and write.
Rev. 1.00 Oct. 01, 2007 Page 1398 of 1956
REJ09B0256-0100