SH7763 Datasheet, PDF (1233/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.13 shows a sample SCIF initialization flowchart.
Start of initialization
Clear TE and RE bits
in SCSCR to 0
[1]
Set TFCL and RFCL bits
in SCFCR to 1 to clear
the FIFO buffer
After reading BRK, DR,
and ER flags in SCFSR, and
ORER flag in SCLSR,
write 0 to clear them
Set CKE1 and CKE0 bits
in SCSCR (leaving TE, RE, TIE, _[2]
and RIE bits cleared to 0)
Set data transfer format
[3]
in SCSMR
Set value in SCBRR
[4]
Wait
No
1-bit interval elapsed?
Yes
Set RTRG1-0 and TTRG1-0 bits
in SCFCR, and clear TFCL
and RFCL bits to 0
Set TE and RE bits in SCSCR
to 1, and set TIE, RIE,
[5]
and REIE bits
[1] Leave the TE and RE bits cleared to 0 until the
initialization almost ends.
[2] Set the CKE1 and CKE0 bits.
[3] Set the data transfer/receive format in SCSMR.
[4] Write a value corresponding to the bit rate into SCBRR.
This is not necessary if an external clock is used.
Wait at least one bit interval after this write before moving
to the next step.
[5] Set the TE or RE bit in SCSCR to 1. Also set the TIE, RIE,
and REIE bits to enable the SCIF_TXD, SCIF_RXD,
and SCIF_CLK pins to be used. When transmitting,
the SCIF_TXD pin will go to the mark state. When
receiving in clocked synchronous mode with the
synchronization clock output (clock master) selected,
a clock starts to be output from the SCIFn_SCK pin
at this point.
End of initialization
Figure 28.13 Sample SCIF Initialization Flowchart
Rev. 1.00 Oct. 01, 2007 Page 1167 of 1956
REJ09B0256-0100