SH7763 Datasheet, PDF (1557/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
35.4 Functional Description
35.4.1 General Functionality
(1) USB Host Module
The USB Host module includes the integrated Root Hub with an external port as well as the List
Processing (LP), the Serial Interface Engine (SIE) and USB clock divider. The interface combines
the responsibility for executing bus transactions requested by the HC as well as the hub and port
management specified by USB. Application interface converts HCI interface to Peripheral bus
interface and SuperHyway bridge bus interface. USB Host module supports OpenHCI registers.
Data transfer is performed on SuperHyway bridge bus interface between External memory and
USB host module. Registers in USB host module are controlled via Peripheral bus interface.
Endpoint Descriptor(ED) and Transfer Descriptor(TD) need to be stored in External memory
before the data transaction begins.
1. List Processor
The List Processor consists of four main blocks. The four blocks are the List Control block, the
ED block, the TD block, and the Request block. The first three blocks operate in a lock step
fashion with the List Control block triggering the ED block, which in turn triggers the TD
block. These blocks are responsible for issuing their own bus master requests to the Request
block which interfaces to the Host Controller Bus Master.
2. Serial Interface Engine (SIE)
The SIE is responsible for managing all transactions to the USB. It controls the bus protocol,
packet generation/extraction, data parallel-to-serial conversion, CRC coding, bit stuffing, and
NRZI encoding.
All transactions on the USB are requested by the List Processor and Frame Manager. After the
List Processor retrieves all information necessary to initiate communication to a USB device, it
generates a request to the SIE accompanied by endpoint-specific control information required
to generate proper protocol and packet formats to establish the desired communication pipe.
The data buffer provides a data path for the data packets and controls the number of bytes
transferred.
The FM generates SOF events each millisecond for which the SIE generates an SOF token.
The List Processor requests are ignored to allow the SOF to be serviced with the highest
priority and without any delay.
Rev. 1.00 Oct. 01, 2007 Page 1491 of 1956
REJ09B0256-0100