SH7763 Datasheet, PDF (1591/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.16 EP0i Data Register (EPDR0i)
EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit
data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in
the trigger register. When an ACK handshake is returned from the host after the data has been
transmitted, EP0iTS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means
of EP0iCLR in the FCLR0 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————
D[7:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R W W W W W W W W
Bit
Bit Name
31 to 8 
7 to 0 D[7:0]
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
Undefined W Data register for control-in transfer
Rev. 1.00 Oct. 01, 2007 Page 1525 of 1956
REJ09B0256-0100