SH7763 Datasheet, PDF (1649/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.10.4 Assigning EP0 Interrupt Sources
The EP0 interrupt sources assigned to IFR0 (bits 0, 1, and 2) must be assigned to the same
interrupt pins by ISR0. The other interrupt sources have no restrictions.
36.10.5 FIFO Clear when DMA Transfer is Set
When the DMA transfer is enabled in endpoint 1, the data register cannot be cleared. Cancel the
DMA transfer before clearing the data register.
36.10.6 Note on Using TR Interrupt
The bulk-in transfer has a transfer request interrupt (TR interrupt). The following points should be
noted when using a TR interrupt.
When the IN token is sent from the USB host and there is no data in the corresponding EP FIFO,
the TR interrupt flag is set. However, the TR interrupt is generated continuously at the timing as
shown in figure 36.20. In this case, note that erroneous operation should not occur.
Note:
When the IN token is received and there is no data in the corresponding EP FIFO, an NAK
is determined. However, the TR interrupt flag is set after an NAK handshake is
transmitted. Therefore when the next IN token is received before TRG/PKTE is written,
the TR interrupt flag is set again.
Rev. 1.00 Oct. 01, 2007 Page 1583 of 1956
REJ09B0256-0100