SH7763 Datasheet, PDF (983/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Initial
Bit
Bit Name Value R/W Description
27
ROCIP
0
R/W Receive Overflow Frame Write-Back Complete
Interrupt Enable
0: Receive overflow frame write-back complete interrupt
is disabled
1: Receive overflow frame write-back complete interrupt
is enabled
26
TABTIP
0
R/W Transmit Abort Detect Interrupt Enable
0: Transmit abort detect interrupt is disabled
1: Transmit abort detect interrupt is enabled
25
RABTIP
0
R/W Receive Abort Detect Interrupt Enable
0: Receive abort detect interrupt is disabled
1: Receive abort detect interrupt is enabled
24
RFCOFIP 0
R/W Receive Frame Counter Overflow Interrupt Enable
0: Receive frame counter overflow interrupt is disabled
1: Receive frame counter overflow interrupt is enabled
23

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
22
ECIIP
0
R/W E-MAC Status Register Source Interrupt Enable
0: E-MAC status interrupt is disabled
1: E-MAC status interrupt is enabled
21
TC0IP
0
R/W Frame Transmission Complete Interrupt Enable
0: Frame transmission complete interrupt is disabled
1: Frame transmission complete interrupt is enabled
20
TDEIP
0
R/W Transmit Descriptor Empty Interrupt Enable
0: Transmit descriptor empty interrupt is disabled
1: Transmit descriptor empty interrupt is enabled
19
TFUFIP
0
R/W Transmit FIFO Underflow Interrupt Enable
0: Underflow interrupt is disabled
1: Underflow interrupt is enabled
18
FRIP
0
R/W Frame Reception Interrupt Enable
0: Frame reception interrupt is disabled
1: Frame reception interrupt is enabled
Rev. 1.00 Oct. 01, 2007 Page 917 of 1956
REJ09B0256-0100