SH7763 Datasheet, PDF (854/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Name
RMII
management
data I/O
Link status
Wake-On-LAN
Port
1
PHY interrupt
GMII transmit
clock
RMII carrier
detection
RMII receive
error
RMII receive
data
RMII receive
data
RMII transmit
enable
RMII transmit
data
RMII transmit
data
RMII carrier
detection (mirror
pin)
RMII receive
error (mirror pin)
RMII receive
data (mirror pin)
RMII receive
data (mirror pin)
RMII transmit
enable (mirror
pin)
Abbreviation
I/O
RMII1_MDIO
I/O
ET1_LINKSTA
ET1_WOL
Input
Output
ET1_PHY-INT
Input
GET1_GTX-CLK Output
RMII1_CRS_DV Input
RMII1_RX_ER Input
RMII1_RXD0
Input
RMII1_RXD1
Input
RMII1_TXD_EN Output
RMII1_TXD0
Output
RMII1_TXD1
Output
RMII1M_CRS_DV Input
RMII1M_RX_ER Input
RMII1M_RXD0 Input
RMII1M_RXD1 Input
RMII1M_TXD_EN Output
Function
Bidirectional signal for exchange of
management information between STA
and PHY in RMII mode
Inputs link status from PHY-LSI
Signal indicating reception of Magic
Packet
Interrupt signal from PHY
Transmit signal timing reference signal in
GMII mode
Carrier detection signal in RMII mode
Identifies error state occurred during data
reception in RMII mode
2-bit receive data in RMII mode
2-bit receive data in RMII mode
Indicates that transmit data is ready on
RMII1_TXD0 and RMII1_TXD1 in RMII
mode
2-bit transmit data in RMII mode
2-bit transmit data in RMII mode
Carrier detection signal in RMII mode
(mirror pin)
Identifies error state occurred during data
reception in RMII mode (mirror pin)
2-bit receive data in RMII mode (mirror
pin)
2-bit receive data in RMII mode (mirror
pin)
Indicates that transmit data is ready on
RMII1_TXD0 and RMII1_TXD1 in RMII
mode (mirror pin)
Rev. 1.00 Oct. 01, 2007 Page 788 of 1956
REJ09B0256-0100