SH7763 Datasheet, PDF (1115/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

11110XX
S SLAVE ADDRESS
R/W A1 SLAVE ADDRESS A2
1st Byte, 7 Bits
0 (Write)
2nd Byte
Section 26 I²C Bus Interface (IIC)
11110XX
Sr SLAVE ADDRESS
R/W A3 DATA A DATA
AP
1st Byte, 7 Bits
1 (read)
Data transferred
(n Bytes + ACKNOWLEDGE)
Figure 26.7 10-Bit Address Data Receive Format
Figure 26.8 shows the data transmit/receive combined format.
In the data transmit/receive combined format, data is transmitted after an address is transmitted
with the first two bytes. Then, the repeated START condition (Sr) is transmitted instead of STOP
condition (P). After Sr is transmitted, the procedure is the same as that in the data receive format.
11110XX
S SLAVE ADDRESS R/W A1 SLAVE ADDRESS A2 DATA A DATA
A/A
1st Byte, 7 Bits
0(Write)
2nd Byte
Data transferred
11110XX
Sr SLAVE ADDRESS
R/W A3 DATA A DATA
1st Byte, 7 Bits
1(Read)
Data transferred
AP
Figure 26.8 10-Bit Address Transmit/Receive Combined Format
Rev. 1.00 Oct. 01, 2007 Page 1049 of 1956
REJ09B0256-0100