SH7763 Datasheet, PDF (643/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
27 to 25 RPT[2:0] 000
R/W DMA Setting Renewal Specify
These bits are enabled in CHCR0 to CHCR3.
000: Normal mode
001: Repeat mode
SAR/DAR/TCR used as repeat area
010: Repeat mode
DAR/TCR used as repeat area
011: Repeat mode
SAR/TCR used as repeat mode
100: Reserved (setting prohibited)
101: Reload mode
SAR/DAR/TCR used as reload area
110: Reload mode
DAR/TCR used as reload area
111: Reload mode
SAR/TCR used as reload area
24
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
23
DO
0
R/W DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR0 to CHCR3.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
22
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
21
DVMD
0
R/W Division Transfer Mode Specification
Specifies the execution of the DMA transfer in 16-byte
units between the on-chip peripheral module STIF and
the external memory.
When the STIF is used, always write 1 to this bit. When
the STIF is not used, always write 0 to this bit.
Rev. 1.00 Oct. 01, 2007 Page 577 of 1956
REJ09B0256-0100