SH7763 Datasheet, PDF (814/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 Compare Match Timer (CMT)
Figure 21.1 shows a block diagram of the CMT.
Pck0
CMSTR
Pre-scaller
CMCNT_0
CMT
CH0
CMCOR_0
CMCSR_0
Pre-scaller
CMCNT_1
Interrupt control
CH1
CMCOR_1
CMCSR_1
Pre-scaller
CMCNT_2
Interrupt control
CH2
CMCOR_2
CMCSR_2
Pre-scaller
CMCNT_3
Interrupt control
CH3
CMCOR_3
CMCSR_3
Pre-scaller
CMCNT_4
Interrupt control
CH4
CMCOR_4
CMCSR_4
Interrupt control
Internal interrupt
DMA transfer
Internal interrupt
DMA transfer
Internal interrupt
DMA transfer
Internal interrupt
DMA transfer
Internal interrupt
DMA transfer
[Legend]
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCNT: Compare match timer counter
CMCOR: Compare match timer constant register
Figure 21.1 Block Diagram of CMT
Rev. 1.00 Oct. 01, 2007 Page 748 of 1956
REJ09B0256-0100