SH7763 Datasheet, PDF (982/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.75 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR)
EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual
bits in the E-MAC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the
corresponding bit.
Bit: 31 30 29 28 27 26 25 24 23
TWB1 TWB0 TC1
IP
IP
IP
TUC
IP
ROC
IP
TABT RABT RFCOF
IP
IP
IP

Initial value: 0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
22
ECI
IP
0
R/W
21
TC0
IP
0
R/W
20
TDE
IP
0
R/W
19
TFUF
IP
0
R/W
18
FR
IP
0
R/W
17
RDE
IP
0
R/W
16
RFE
IP
0
R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





DLC CD TRO RMAF CEEF CELF RRF RTLF RTSF PRE CERF
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31
TWB1IP 0
R/W Write-Back Complete Interrupt Enable
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
30
TWB0IP 0
R/W Write-Back Complete Interrupt Enable
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
29
TC1IP
0
R/W Frame Transmission Complete Interrupt Enable
0: Frame transmission complete interrupt is disabled
1: Frame transmission complete interrupt is enabled
28
TUCIP
0
R/W Transmit Underflow Frame Write-Back Complete
Interrupt Enable
0: Transmit underflow frame write-back complete
interrupt is disabled
1: Transmit underflow frame write-back complete
interrupt is enabled
Rev. 1.00 Oct. 01, 2007 Page 916 of 1956
REJ09B0256-0100